1. Field of the Invention
This invention relates to non-volatile semiconductor memory device, and more particularly to a semiconductor memory device in which a method of application of signals to a sense amplifier is able to read data from memory cells such as flash memories at high speed.
2. Discussion of the Related Art
Recently, attention has been paid to non-volatile semiconductor memories such as mask ROMs, PROMs (Programmable ROM), EPROMs(Erasable and Programmable Read Only Memories) and EEPROMs (Electrical Erasable and Programmable Read Only Memories) in ROMs(Read Only Memory) as a kind of LSI Memory. In the EPROM or the EEPROM, charges are stored in the floating gate and the variation of the threshold voltage due to the presence or absence of charges is detected with the control gate to read and write the data. An example of the EEPROM is a flash EEPROM(flash memory), in which the data of the whole memory chip are erased, or the memory cell array is divided into an optional number of blocks, and in each of the blocks the data are erased.
Memory cells forming the flash EEPROM are roughly divided into split gate type ones and stack gate type ones.
The split gate type flash EEPROM is disclosed by "WO92/18980 (G11C 13/00)".
FIG. 2 is a sectional view of the split gate type flash EEPROM disclosed by "WO92/18980".
As shown in FIG. 2, an N-type source S and an N-type drain D are formed on a P-type single crystal silicon substrate. On a channel CH between the source S and the drain D, a floating gate FG is formed through a first insulating film 103. On the floating gate FG, a control gate CG is formed through a second insulation film 104. A part of the control gate CG is formed through a first insulating film 103 on a channel CH, thus forming a selecting gate 105.
The arrangement of the above-described flash memory is as shown in FIG. 7.
In FIG. 7, a common word line 3 is coupled to nonvolatile flash memory cells 1 and 2, and bit lines 4 and 5 are independently connected. The bit lines 4 and 5 . . . are combined together by I/O line 10. And a predetermined pre-charge voltage is applied to the bit lines 4 and 5 . . . through a N channel MOS transistor 18. One end of the N channel MOS transistor is connected to the source voltage (V.sub.DD), and other end of that is connected to I/O line 10. The bit lines 4 and 5 have N-channel MOS transistors 8 and 9 which are driven by column lines 6 and 7 . . . , respectively.
The bit lines 4 and 5 are combined together by I/O line 10, and connected to a sense amplifier 11 using a current mirror circuit. When an N-channel MOS transistor 12 is turned on in response to a sense signal (read-out signal), the sense amplifier 11 is activated.
It is assumed that it is the sense time, and the column line 6 is selected, and the N-channel MOS transistor 8 is turned on and the memory cell 1 is in "on" state. The N-channel MOS transistor 12 is turned on by the sense signal, and the sense amplifier 11 operates, and a P-channel MOS transistor 14 which applies a bias current to the memory cell is turned on, so that current flows in the memory cell 1. As a result, the voltage of the I/O line 10 is decreased towards the ground level. When the voltage of the I/O line 10 is decreased, the transistor 15 tends to be "off" and the transistor 14 also tends to be "off". As a result, the transistor 15 is turned off, and the transistor 16 is tuned on.
Accordingly, an amplified "L" level signal is provided at an output terminal 17.
In the case where the memory cell 1 is in "off" state (programmable state), the same operation occurs in inverse polarity, so that an amplified "H" level signal is provided at the output terminal 17.
Hence, according to the circuit of FIG. 7, the flash memory data can be amplified while being read out.
However, the circuit of FIG. 7 suffers from the problem that it takes time to read out data. That is, in the circuit of FIG. 7, in order to obtain a signal level necessary for inverting the differential amplifier forming the sense amplifier 11, it is necessary to flow a predetermined amount of current to the memory cell, taking a predetermined period of time. This predetermined period of time cannot be controlled by the designer, and of all the cells, the longest time one is the standard value of the product, and therefore the time is unstable and slow.